DocumentCode :
438407
Title :
Bridging fault testability of BDD circuits
Author :
Shi, Junhao ; Fey, Görschwin ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Bremen Univ., Germany
Volume :
1
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
188
Abstract :
In this paper we study the testability of circuits derived from binary decision diagrams (BDDs) under the bridging fault model. It is shown that testability can be formulated in terms of symbolic BDD operations. By this, test pattern generation can be carried out in polynomial time. A technique to improve testability is presented. Experimental results show that a complete classification can be carried out very efficiently.
Keywords :
automatic test pattern generation; binary decision diagrams; fault diagnosis; logic circuits; logic testing; BDD circuits; binary decision diagrams; bridging fault model; fault testability; polynomial time; symbolic BDD operations; test pattern generation; Binary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Computer science; Data structures; Delay; Libraries; Polynomials; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466155
Filename :
1466155
Link To Document :
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