Library cell layout with Alt-PSM compliance and composability

The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many resolution enhancement techniques (RET). The difficulty and feasibility of deploying the RET such as alternating phase shifting mask (Alt-PSM) depend heavily on circuit layout. In this paper, we propose a Boolean satisfiability (SAT) based library cell layout method that can achieve Alt-PSM compliance and composability in a constructive manner. Compared to previously reported post processing approach, our method often leads to further cell area efficiency improvement.