DocumentCode
438430
Title
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness
Author
Jiang, Tui-Ying ; Liu, Chien-Nan Jimmy ; Jou, Jing-Yang
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
323
Abstract
Simulation based validation approaches are still the primary workhorse for solving the verification problem of getting the initial HDL description correct, especially for large scaled designs. However, most of existing code coverage metrics do not address observability issue (Fallah et al., 2001). Therefore, we intend to provide additional observability measures to statement coverage metric for more proper and realistic evaluation of verification completeness for a HDL design. As compared to OCCOM (Fallah et al., 1998; Fallah et al., 2001; Devadas et al., 1996), our approach estimates a real probabilistic likelihood of propagating erroneous effects without any unreasonable assumptions and can always provide lower bound estimation.
Keywords
formal verification; hardware description languages; logic design; observability; HDL description; HDL design; hardware description language; observability measure; simulation based validation; statement coverage metric; verification completeness; Design engineering; Digital circuits; Electric variables measurement; Formal verification; Hardware design languages; Observability; State estimation; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466182
Filename
1466182
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