DocumentCode
438458
Title
Scalable interprocedural register allocation for high level synthesis
Author
Beidas, Rami ; Zhu, Jianwen
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
511
Abstract
The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the departure from the industrial standard, register transfer level design methodology. Recent advances of micro-architecture model enabled the use of stacked based controller, allowing complex algorithms with multiple procedures to be implemented directly in hardware. Nevertheless, design optimizations across procedure boundaries have not been fully explored. In this paper, we address the problem of interprocedural register allocation in the context of high level synthesis. In contrast to a recently proposed interprocedural register allocation algorithm, which processes an expensive, global, graph representation of the conflict relation of all values to achieve near optimally, we introduce a new method, called color palette propagation (CPP). The key idea behind our method, is to propagate the use of colors, whose number is significantly smaller than the size of the conflict relation, across different procedures. With a complexity comparable to intraprocedural register allocation, we show that our method can scale to very large C programs. For those benchmarks that can be handled by conventional global methods, our method produced nearly the same number of registers, while providing an average speedup factor of 90.
Keywords
circuit optimisation; high level synthesis; integrated circuit design; storage allocation; C programs; color palette propagation; design optimizations; high level synthesis; intraprocedural register allocation; microarchitecture model; register transfer level design; scalable interprocedural register allocation; stacked based controller; Application software; Color; Computer industry; Costs; Design methodology; Design optimization; Hardware; High level synthesis; Job shop scheduling; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466217
Filename
1466217
Link To Document