DocumentCode :
438480
Title :
Leakage control in FPGA routing fabric
Author :
SRINIVASAN, SUDARSHAN ; Gayasen, A. ; Vijaykrishnan, N.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Volume :
1
fYear :
2005
fDate :
18-21 Jan. 2005
Firstpage :
661
Abstract :
As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.
Keywords :
field programmable gate arrays; logic design; network routing; 65 nm; FPGA routing fabric; interconnect fabric; leakage control; leakage power reduction; multiplexer; Computer science; Design engineering; Fabrics; Field programmable gate arrays; Integrated circuit interconnections; Logic; Multiplexing; Routing; Sleep; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
Type :
conf
DOI :
10.1109/ASPDAC.2005.1466246
Filename :
1466246
Link To Document :
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