A 74dB dynamic range, 1.1-MHz signal band 4th-order 2-1-1 cascade multi-bit CMOS Σ Δ modulator for ADSL

This paper explores the use of ΣΔ techniques for A/D conversion exceeding 1-MHz signal bandwidth. A cascade modulator architecture is proposed which combines single-bit and multi-bit quantization to obtain more than 12-b Dynamic Range (DR) with an oversampling ratio of only 16, and with neither calibration nor trimming required. Measurements from a 0.7µm CMOS prototype show 74dB DR in 1.1-MHz signal band at 35.7- MHz clock rate, with a power consumption of 55mW from a 5-V supply.