Title :
2.5Gb/s ATM physical layer controller in 0.8 µm BiCMOS
Author :
Hansen, F. ; Salama, C.A.T.
Author_Institution :
University of Toronto, Toronto, Ontario, Canada
Abstract :
This paper presents two integrated circuits which together form a complete Physical Layer (PL) for 2.5Gb/s ATM. The two circuits are a Clock and Data Recovery unit with integrated demultiplexer, and a complex Transmission Convergence unit. The two circuits are manufactured in the same 0.8µm BiCMOS process, and could easily be combined to provide a single-chip solution.
Keywords :
BiCMOS integrated circuits; Clocks; Convergence; Phase frequency detector; Phase locked loops; Physical layer; Telecommunication traffic; Transconductance; Very large scale integration; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
Conference_Location :
Southampton, UK
