Title :
A 3.3V power adaptive 1244/622/155 Mb/s transceiver for ATM, SONET/SDH
Author :
Belot, D. ; Dugoujon, L. ; Dedieu, S.
Author_Institution :
SGS-Thomson Central R&D, Crolles, France
Abstract :
A multi-rate 155/622/1244 Mbit/s Transceiver for ATM & SDH/SONET [1] is described. It includes 3 PLLs with 1.24GHz VCOs without need for external trimming. Wafer-test of the whole core is made available. Power Adaptation from 550mW @ 155Mbit/s to 1W @ 1.24Gbit/s is achieved by use of a specific programmable ECL library. Analog HDL Top-down approach was validated to speed-up development and increase reusability.
Keywords :
Asynchronous transfer mode; Circuits; Clocks; Cost function; Frequency; Phase locked loops; SONET; Synchronous digital hierarchy; Transceivers; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
Conference_Location :
Southampton, UK
