DocumentCode
439187
Title
A 12bit medium-time analog storage device in a CMOS standard-process
Author
Ehlert, Martin ; Klar, Heinrich
Author_Institution
Technical University of Berlin, Berlin, Germany
fYear
1997
fDate
16-18 Sept. 1997
Firstpage
160
Lastpage
163
Abstract
A new 12bit medium-time analog storage device is presented. The proposed circuit is based on a fully differential two-stage operational amplifier (OPAMP) working as Sample and Hold circuit (S&H). A novel refresh-scheme employing Common-Mode-Rejection has been developed which extends the storage time on a capacitance beyond the border of voltage decay caused by charge leaking. Measurements show 12bit and 8bit resolution for 15s and 330s respectively. The circuit is intended for use in Analog Neural Networks. The basic idea can be extended to design simple low-cost S&H circuits.
Keywords
CMOS technology; Capacitance; Circuits; Clocks; IEEE members; Leakage current; Resistors; Sampling methods; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
Conference_Location
Southampton, UK
Type
conf
Filename
1470888
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