A 200 MHz cell for a parallel-successive-approximation ADC in 0.8 µm CMOS, using a reference pre-select scheme

A Successive-Approximation A/D converter cell for a Parallel-SA-ADC is presented. The ADC cell uses a Reference Pre-Select scheme, in order to minimize the decision loop in every binary search step, and make a high frequency operation possible. In binary search, we know that next step is to look at one of two possible references. This is utilized in three steps and the critical decision loop is minimized to "amplify the analog input to a digital signal and open one of two possible switches". A comparator with differential return to zero output is developed for the fast decision loop. Measurements of a partly working test chip shows that 10 bits resolution at 200 MHz is possible. The ADC cell consumes 75 mW.