A 103MHz open-loop full CMOS highly-linear sample-and-hold amplifier

Based on a novel highly-linear cascode-driver CMOS source-follower buffer, we have designed a very high speed sample-and-hold circuit in a 0.8µm digital CMOS process. The circuit achieves -61dB THD at a sampling rate of 103MHz, while a 1.4Vp-p20 MHz input signal is applied. The high performance of the circuit is mainly due to its open-loop buffers and its fully differential structure.