Title :
200 megasample per second 6 bit A/D converter
Author_Institution :
GEC Plessey Semiconductors, Scotts Valley, USA
Abstract :
A 200 Megasample per second flash A/D converter was built on a standard digital 5V 0.6µ CMOS process in an area of 1.5 square millimeters. The effects of metastability and bubbles were addressed to achieve a low error rate of 1e-9.
Keywords :
CMOS process; Capacitors; Decoding; Error analysis; Latches; MOS devices; Metastasis; Read only memory; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
Conference_Location :
Southampton, UK
