Serial interface macrocells for 2.5 Gb/s in 0.35 µm CMOS

Architecture and macrocells for ASICs with an arbitrary number of 2.488 Gb/s serial links are realized in a 0.35µm standard digital CMOS technology. Fed by a halfclock distribution system, the macrocells transfer serial data to a 16b parallel format, which can be handled by standard cell logic, and vice versa. The macrocells were assembled on a 5.3×5.1 mm testchip together with auxiliary logic, and are working up to 2.9 Gb/s in a real-world environment.