A 5.2 nS cycle time floating point unit macrocell

This paper describes the structured custom design of a pipelined floating point unit (FPU) macrocell. The core of the floating point unit is a multiplier-accumulator (MAC) block which can execute a 2 clock cycle addition, subtraction or multiplication, or, a 4 cycle multiply-accumulate operation. The floating point unit supports both floating point and signed integer arithmetic, as well as, float-to-int, int-to-float, and, float-to-float conversions between different mantissa widths. The simulated cycle time for the FPU with typical process parameters at 3.3 V and 85° C is 5.2 nS. The rapid completion of the design was made possible by leveraging an existing generator based datapath module library. Approximately 25 man months were required from initial customer specification until final physical assembly of the structured custom block. The floating point unit is implemented with 165,000 transistors in a 0.35µm, 4 metal CMOS process and occupies 2.45 mm × 2.55 mm.