A multi-bit Σ Δ modulator in floating body silicon-on-sapphire CMOS technology for extreme radiation environments

This paper presents the design of a first order ΣΔ modulator with 4-bit internal qunatisation, fabricated in a 1.5µm radiation hard partially depleted silicon-on-sapphire digital CMOS process. Both the architecture and the circuit design are optimised using a variety of unconventional techniques to account for the influence of extreme bias-dependent radiation induced threshold voltage shifts of up to 1V, as well as poor 1/f device noise. In addition, the circuitry is specially adapted to accommodate the floating body behaviour of this type of process, wherein drain conductance varies considerably with drain bias and frequency. These techniques are directly applicable to VLSI SOI design, where similar device physics are encountered. The circuit provides 9.7 bits of dynamic range in a 63kHz signal bandwidth, only degrading to 9.1 bits after 23Mrad(Si) of total dose γ radiation.