DocumentCode :
439331
Title :
A sub-binary-weighted current calibration technique for a 2.5V 100MS/s 8bit ADC
Author :
Mitsuishi, M. ; Yoshida, H. ; Sugawara, M. ; Kunisaki, Y. ; Nakamura, S. ; Nakaigawa, S. ; Suzuki, H.
Author_Institution :
NEC Corporation, Kanagawa, Japan
fYear :
1998
fDate :
22-24 Sept. 1998
Firstpage :
420
Lastpage :
423
Abstract :
Sub-binary-weighted current circuits make possible low-power and small-area calibration circuits for a low-supply-voltage two-step subranging analog-to-digital converter (ADC). Placed in the calibration circuits, they can be 71% smaller than conventional replica circuits. Moreover, they make it possible to calibrate only one time before A/D conversions, because they can hold the calibrated data during A/D conversions. Consequently, the mean power of calibration circuits can be greatly reduced. The power dissipation of calibration circuits during A/D conversions is only 0.5 mW, and the area is 0.036 mm2, which is 2.3% of the ADC core. The effectiveness of this technique has been demonstrated with a 2.5V 100MS/s 8bit ADC.
Keywords :
Analog-digital conversion; Calibration; Circuits; Error correction; Laboratories; National electric code; Power dissipation; Shape; Ultra large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Conference_Location :
The Hague, The Netherlands
Type :
conf
DOI :
10.1109/ESSCIR.1998.186298
Filename :
1471055
Link To Document :
بازگشت