• DocumentCode
    439334
  • Title

    VLIW architectures for low-power processors: A first evaluation

  • Author

    Puiatti, J.-M. ; Sanchez, E. ; Piguet, C. ; Llosa, J.

  • Author_Institution
    Swiss Federal Institute of Technology, Lausanne, Switzerland
  • fYear
    1998
  • fDate
    22-24 Sept. 1998
  • Firstpage
    436
  • Lastpage
    439
  • Abstract
    In this paper, we evaluate the possibility of designing a high-performance, low-consumption 8b or 16b microcontroller. More precisely, we investigate whether the instruction-level parallelism (ILP) architectures (e.g., superscalar or VLIW) used in high-performance, high-consumption processors can be adapted to low-power, high-performance 8b or 16b microcontrollers. In order to quantify the potential improvements that can be obtained by these kinds of parallel architectures, we make a comparison between low-power scalar processors and low-power ILP processors in terms of both performance and energy efficiency.
  • Keywords
    Complexity theory; Computer architecture; Energy consumption; Energy efficiency; Frequency; Microcontrollers; Parallel architectures; Parallel processing; Pipeline processing; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
  • Conference_Location
    The Hague, The Netherlands
  • Type

    conf

  • DOI
    10.1109/ESSCIR.1998.186302
  • Filename
    1471059