• DocumentCode
    439335
  • Title

    Hardware for computing modular multiplication algorithm

  • Author

    Bernal, Alvaro ; Guyot, Alain

  • Author_Institution
    TIMA Laboratory, Grenoble, France
  • fYear
    1998
  • fDate
    22-24 Sept. 1998
  • Firstpage
    444
  • Lastpage
    447
  • Abstract
    This paper examines the characteristics of an alternative architecture for computing a modular multiplication based on Montgomery´s algorithm, useful in performing the RSA Public Key Cryptosystems. An experimental 12×12 bits modular multiplier prototype has been designed with this architecture. Is fabricated by AMS using 0.6 µm-CMOS technology. The architecture, its operation and some simulation results are presented. The evaluation is provided according to the functionality. The active area size is 1.33 × 0.93 mm2containing a number of transistors about 4100.
  • Keywords
    Adders; Arithmetic; Circuit simulation; Computational modeling; Computer architecture; Hardware; Laboratories; Prototypes; Public key cryptography; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
  • Type

    conf

  • DOI
    10.1109/ESSCIR.1998.186304
  • Filename
    1471061
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439335