Hardware for computing modular multiplication algorithm

This paper examines the characteristics of an alternative architecture for computing a modular multiplication based on Montgomery´s algorithm, useful in performing the RSA Public Key Cryptosystems. An experimental 12×12 bits modular multiplier prototype has been designed with this architecture. Is fabricated by AMS using 0.6 µm-CMOS technology. The architecture, its operation and some simulation results are presented. The evaluation is provided according to the functionality. The active area size is 1.33 × 0.93 mm²containing a number of transistors about 4100.