A 1-V 20-ns 512-Kbit MT-CMOS SRAM with auto-power-cut scheme using dummy memory cells

A 512-Kbit SRAM using dual threshold voltage transistors has been fabricated. The memory cells are composed of high-threshold voltage transistors and cutting off the power supply to the peripheral circuit reduces the power consumption without data destruction during sleep mode. The SRAM adopts a current-mirror type sense-amplifier circuit for fast access. An autopower-cut circuit automatically cuts off the current to the sense-amplifier circuit after the read operation is finished. The SRAM has a 20 ns access time, a 23.5 mW active power consumption at 10 MHz and a less than 10 µW sleep power consumption with a 1 V power supply.