Title :
Madematching: Methodology and tool for matching simulation
Author :
Janssens, Er. ; Graindourze, B. ; Casier, H.
Author_Institution :
Alcatel Microelectronics, Brussels, Belgium
Abstract :
A methodology and tool is presented, which enables the designer to simulate the influence of random offset variations on his circuit without any manual calculation. The starting point is a schematic and extra information on the transistor layout and the result is a report on the total random offset and a list of its main components.
Keywords :
Analytical models; Capacitance; Circuit simulation; Circuit topology; Erbium; Integrated circuit technology; Low voltage; Microelectronics; Monte Carlo methods; Sensitivity analysis;
Conference_Titel :
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
DOI :
10.1109/ESSCIR.1998.186318
