DocumentCode
439365
Title
14-bit, 2.2MS/s sigma delta ADCs
Author
Morizio, J. ; Hoke, M. ; Kocak, T. ; Geddie, C. ; Hughes, C. ; Perry, J. ; Madhavapeddi, S. ; Hood, M. ; Lynch, G. ; Kondoh, H. ; Kumamoto, T. ; Okuda, T. ; Noda, H. ; Ishiwaki, M. ; Miki, T. ; Nakaya, M.
Author_Institution
Mitsubishi Electric America, Durham, NC
fYear
1999
fDate
21-23 Sept. 1999
Firstpage
82
Lastpage
85
Abstract
This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.
Keywords
Consumer electronics; Delta modulation; Delta-sigma modulation; Digital modulation; Energy consumption; Error correction; Noise shaping; Power dissipation; Quantization; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
Conference_Location
Duisburg, Germany
Type
conf
Filename
1471101
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