• DocumentCode
    439366
  • Title

    A 13.5-bit cost optimized multi-bit delta-sigma ADC for ADSL

  • Author

    Wiesbauer, A. ; Weinberger, H. ; Clara, M. ; Hauptmann, J.

  • Author_Institution
    Infineon Technology Austria, Villach, Austria
  • fYear
    1999
  • fDate
    21-23 Sept. 1999
  • Firstpage
    86
  • Lastpage
    88
  • Abstract
    A high-resolution multi-bit ΣΔ ADC architecture for operation at low oversampling ratios is introduced. An area-efficient implementation of a 3rd-order 7-bit modulator, avoiding pipeline latency effects, is presented. Clocked at 26 MHz, the 0.6µm CMOS, dual-stage ΣΔ ADC achieves 83 dB SNR over a 1.1 MHz signal bandwidth.
  • Keywords
    Bandwidth; Clocks; Cost function; Delay; Logic; Noise cancellation; Operational amplifiers; Pipelines; Quantization; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
  • Conference_Location
    Duisburg, Germany
  • Type

    conf

  • Filename
    1471102
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439366