• DocumentCode
    439371
  • Title

    2.44 GFLOPS 300MHz floating-point vector processing unit for high performance 3D graphics computing

  • Author

    Nobuhiro Ide ; Hirano, Masahiro ; Yukio Endo ; Yoshioka, Shohei ; Murakami, H. ; Kunimatsu, A. ; Sato, T. ; Kamei, T. ; Okada, T. ; Suzuoki, M.

  • Author_Institution
    Toshiba Corporation, Kawasaki, Japan
  • fYear
    1999
  • fDate
    21-23 Sept. 1999
  • Firstpage
    106
  • Lastpage
    109
  • Abstract
    A Vector Unit (VU) for the high performance 3D graphics computing has been developed. Four fMAC (floating-point Multiply-Accumulate) units which execute multiply-add operation with one throughput, one fDIV (floating-point Divide) unit which executes division and square root operations with 6 cycles at 300 MHz and 128 bits × 32 words fReg (floating-point register file) are implemented. This architecture delivers a peak performance of 2.44 GFLOPS at 300MHz.
  • Keywords
    Computer architecture; Computer graphics; Concurrent computing; Delay; High performance computing; Laboratories; Pipelines; Systems engineering and theory; Throughput; Ultra large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
  • Conference_Location
    Duisburg, Germany
  • Type

    conf

  • Filename
    1471107
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439371