DocumentCode :
439387
Title :
A 15-bit pipelined floating-point A/D converter
Author :
Thompson, D.U. ; Wooley, B.A.
Author_Institution :
Stanford University, Stanford, CA
fYear :
1999
fDate :
21-23 Sept. 1999
Firstpage :
170
Lastpage :
173
Abstract :
A 15-bit switched-capacitor pipelined floating-point A/D converter (FADC) has been designed with a 5-bit exponent and a 10-bit mantissa. The exponent value is established by a 3-stage pipelined variable gain amplifier, while the mantissa is determined with a 10-bit uniform pipelined A/D converter. An experimental prototype of the converter has been implemented in a 0.5-µm CMOS technology. It achieves a dynamic range of 15 bits at a conversion rate of 20Msamples/sec with a total power dissipation of 380mW.
Keywords :
Analog-digital conversion; CMOS technology; Calibration; Dynamic range; Gain; Instruments; Physics; Power dissipation; Signal resolution; Switching converters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
Conference_Location :
Duisburg, Germany
Type :
conf
Filename :
1471123
Link To Document :
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