An 8-bit low-voltage pipelined ADC utilizing switched-opamp technique

A low-voltage 8-bit pipelined analog-to-digital converter employing the switched-opamp technique is presented. The developed low-voltage circuit blocks include a fully differential switched-opamp, a multiplying digital-to-analog converter (MDAC), a comparator and a front-end input buffer. The circuit is implemented in a standard 0.5 µm CMOS process. According to measurements the circuit achieves a 44.7 dB peak SNDR at 8 MHz clock rate. The circuit operates with supply voltages down to 1.0 V