Title :
A CMOS 10bit 37MS/s pipelined A/D converter with code regeneration and averaging
Author :
Lee, Beaung Woo ; Cho, Gyu Hyeong
Author_Institution :
Korea advanced Institute of Science and Technology, Taejon, Korea
Abstract :
A 10bit pipelined analog to digital converter(ADC) having 1bit per stage architecture with code regeneration is proposed. Code regeneration is performed by digital averaging of two analog shifted codes obtained from one sample of analog input to ADC. Analysis shows allowable gain and offset errors are tolerable up to 8bit resolution to achieve 10bit ADC. This allows ADC free from calibration or trimming against gain errors to implement 10bit resolution. Test results show that the maximum DNL of 0.51LSB and 37MHz conversion rate with the process of 0.8µm CMOS.
Keywords :
Aging; Analog-digital conversion; CMOS process; CMOS technology; Calibration; Circuits; Degradation; Error correction; Logic; Testing;
Conference_Titel :
Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
Conference_Location :
Duisburg, Germany
