Title :
ECL-CMOS logic LSI technology using 20 GHz latch with CMOS test circuits
Author :
Yabuki, Shinobu ; Hayashi, Atsuhiro ; Ito, Yuko ; Maruyama, Tetsuya ; Okada, Hidehiro ; Usami, Masami ; Higeta, Keiichi ; Hamamoto, Masato ; Isomura, Satoru
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
An ECL-CMOS LSI for computing and communication including 280k ECL gates and 1Mbit RAM is developed with Advanced CMOS ECL Technology, which uses seven layer metallization including copper damascene and SGI/U-Isolation with SOI wafer. Used latch with CMOS test circuits has 20GHz toggle frequency and highly detectable delay test is possible.
Keywords :
CMOS logic circuits; CMOS technology; Circuit testing; Copper; Delay; Frequency; Large scale integration; Latches; Logic testing; Metallization;
Conference_Titel :
Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
Conference_Location :
Duisburg, Germany
