A 73dB SFDR 10.7MHz 3.3V CMOS bandpass Σ Δ modulator sampled at 37.05MHz

This paper examines the design and the implementation of a 6th-order bandpass ΣΔ modulator to be used for IF sampling at 10.7MHz of the FM radio signal. The modulator is sampled at 37.05MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a double-poly 0.35µm CMOS technology using Switched Capacitor (SC) technique and consumes 116mW from a single 3.3V power supply. The modulator features 75dB dynamic range and 66dB peak-SNR within a 200kHz bandwidth (FM bandwidth). Third order intermodulation products are suppressed by -78dBc.