DocumentCode :
439476
Title :
A low power reconfigurable 12-tap FIR interpolation filter with fixed coefficient sets
Author :
Henning, C. ; Schwann, R. ; Gierenz, V. ; Noll, T.G.
Author_Institution :
University of Technology RWTH Aachen, Germany
fYear :
2000
fDate :
19-21 Sept. 2000
Firstpage :
81
Lastpage :
84
Abstract :
A parameterizable architecture of a low power FIR interpolation filter with reconfigurable coefficient sets for timing phase alteration is presented. For the application in a handheld ultrasound scanner, the filter has been optimized for lowest power dissipation on all levels of CMOS design from system down to physical layout level. The architecture is well suited for a datapath generator design offering full-custom performance at lowest design effort. A test chip integrating a 6/12-tap filter has been realized in a 0.5-µm CMOS technology for a clock frequency of 40 MHz featuring a power dissipation as small as 0.9 mW per tap.
Keywords :
CMOS technology; Clocks; Design optimization; Finite impulse response filter; Interpolation; Power dissipation; Power filters; Testing; Timing; Ultrasonic imaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location :
Stockholm, Sweden
Type :
conf
Filename :
1471218
Link To Document :
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