Title :
ItaniumTMprocessor system bus design
Author :
Ilkbahar, Alper ; Venkataraman, Srinivas ; Muljono, Harry
Author_Institution :
Intel Corporation, Santa Clara, CA, United States
Abstract :
This paper presents the design of the ItaniumTMProcessor´s system bus interface achieving a peak data bandwidth of 2.1GB/s in a glue-less 4-way multiprocessing system. A source-synchronous data bus with differential strobes enables this high bandwidth. Topics covered in this paper include optimisation technique for the system topology, CPU package, signalling protocol and I/O circuits. Highly accurate modelling and validation methodologies enable a good correlation of experimental results with simulation data.
Keywords :
Bandwidth; Central Processing Unit; Circuit topology; Clocks; Driver circuits; Integrated circuit interconnections; Packaging; Process design; System buses; Termination of employment;
Conference_Titel :
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location :
Stockholm, Sweden
