Analog design in deep sub-micron CMOS

Analog design in deep sub-micron technologies is a reality now and poses severe challenges to the circuit designer. Trends in technologies as well as circuit design are discussed. It is shown that the power required for a certain dynamic range and bandwidth decreases with minimum feature size as long as a constant ratio between signal swing and supply voltage can be maintained. Below 0.1µm channel-length, predictions of the threshold voltage endanger that requirement however. At circuit level, the problem that a low supply voltage poses on the use of switches and amplifiers is discussed. Various techniques are discussed to overcome these problems, like the use of low Vthtransistors, clock boosting, switched OpAmp technique, rail-to-rail input stages, back-gate driving circuits and CM level-shift techniques. Based on power estimates, the necessity of matching enhancing techniques like Auto-Zero techniques and Averaging is shown.