Title :
A 2.5 volt 6 bit 600MS/s flash ADC in 0.25 µm CMOS
Author_Institution :
Philips Research Laboratories Eindhoven, Eindhoven, the Netherlands
Abstract :
A 2.5V high speed 6 bits flash analog-to-digital converter for storage read channels is presented. Offset voltages in the distributed amplifiers are averaged to improve DNL and INL performance. An end-load circuit is designed to act as a characteristic termination, to prevent the bending of the output curve. The ADC is implemented in a single supply voltage, 0.25µm standard digital CMOS process, and consumes 193mW.
Keywords :
CMOS process; Capacitance; Circuit simulation; Circuits and systems; Intelligent networks; Laboratories; Linearity; Resistors; Signal processing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location :
Stockholm, Sweden
