DocumentCode
439517
Title
A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter
Author
Lee, Chang-Hyeon ; McClellan, Kelly ; Choma, John, Jr.
Author_Institution
Conexant Systems, Inc., Newport Beach, CA
fYear
2000
fDate
19-21 Sept. 2000
Firstpage
256
Lastpage
259
Abstract
A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using a capacitive DC-DC converter (VRCC) achieves a jitter level of 30ps rms for quiet supply, and 42ps rms for 600mV supply noise, with a locking range of 110MHz to 850MHz. The worst case PSNR using VRCC shows -45dB in the medium frequency. The circuit is fabricated in a 0.35µm, 3.3V standard digital CMOS process and occupies 2.2mm2. The power consumption at 3.3V including buffer is 42mW at 500MHz.
Keywords
CMOS process; Circuit noise; DC-DC power converters; Frequency; Jitter; Noise level; PSNR; Phase locked loops; Regulators; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location
Stockholm, Sweden
Type
conf
Filename
1471260
Link To Document