DocumentCode
439542
Title
Investigation of cell leakage and data retention in eDRAM
Author
Hashimoto, Masashi ; Baumann, Robert
Author_Institution
Cadence Design Systems, Yokohama, Japan
fYear
2000
fDate
19-21 Sept. 2000
Firstpage
356
Lastpage
359
Abstract
A charge offset scanning method of determining individual cell leakages in DRAM devices is described. The leakage behaviour of cells from the main and tail distributions is compared and the results of data retention studies on a 0.5µm CMOS embedded DRAM technology for ASIC applications are also discussed. An order of magnitude improvement in the retention time of the tail bits was achieved as an outcome of the study.
Keywords
Application specific integrated circuits; CMOS technology; Capacitance; Current measurement; Equations; Probability distribution; Random access memory; Semiconductor device measurement; Time measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location
Stockholm, Sweden
Type
conf
Filename
1471285
Link To Document