Investigation of cell leakage and data retention in eDRAM

A charge offset scanning method of determining individual cell leakages in DRAM devices is described. The leakage behaviour of cells from the main and tail distributions is compared and the results of data retention studies on a 0.5µm CMOS embedded DRAM technology for ASIC applications are also discussed. An order of magnitude improvement in the retention time of the tail bits was achieved as an outcome of the study.