A low-power SRAM with resonantly powered data, address, word, and bit lines

We present a low-power SRAM based on resonantly powered data-in, data-out, address, word, and bit lines. The clock rails power these lines from a two-phase resonant driver. The measured core dissipation for a 256 × 16 bit, 0.5 µm nwell CMOS prototype chip is 2.7 mW at 51.3 MHz. The core supply voltage is 2.0 V and the resonant driver voltage is 0.8 V. The clock voltage swing is 2.1-2.2 V. The core size is 1.57 mm × 1.54 mm.