A skew-tolerant design scheme for over 1-GHz LSIs

We have developed a circuit design which uses heterogeneous pipelines and latches to maximize hidable clock skew and jitter. With it, the hidable portion of the sum of clock skew and jitter is as large as a fourth of cycle time. In 0.15-µm CMOS LSIs of 500-MHz and 1- GHz based on our new design, performance was, respectively, 22% and 66% better than that of similar FF-based LSIs. We have also developed a 64-b floating-point multiplier that incorporates high-speed dual-rail domino logic into our design and have fabricated it using 0.25-µm CMOS process technology.