New fast-lock PLL for mobile GSM GPRS applications

This paper presents a new Fast-Lock synthesizer for the recent GSM evolution GPRS, HSCSD and EDGE. The concept provides half the lock-in time of a common integer-N PLL with state-of-the-art phase noise and improved spurious suppression. Measurements of a high integrated GSM transceiver using the Fast-Lock concept show a sufficient lock-in time for the new standards. The PLL functional block can easily be used in large scale integrated GSM-transceivers for the next generation of GSM mobiles.