An analogue delay line for virtual clock enhancement in DDS

In this paper we describe an analogue delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method consists in an immediate application of the output signal of the phase accumulator for the generation of the desired frequency. In contrast to the conventional approach of frequency generation by means of DDS the use of a fast ROM for storing the sine table and a DAC will be avoided. To get the necessary spectral purity of the generated frequency additional digital signal processing (DSP) based on a delay-locked loop (DLL), dithering and noise shaping is applied. The realisation of the DLL and the consequences of non-linear effects within the DL to the spectral performance of the DDS are explained.