Integrated offset trimming technique

Great accuracy requirements on new analog circuit generations push analog IC suppliers to develop improved circuit architecture and trimming techniques. We propose in this paper a new post packaging technique based on the use of snap back transistor associated to specific control structure. Fully compatible with the initial pin out of the circuit this technique is validated on a specific amplifier used as a demonstrator and integrated in a 0.7µm BiCMOS process. Example of post packaging offset reduction is given on a batch of 50 circuits.