A low jitter digital timing synchronizer for CAP-based VDSL system

This paper presents a digital timing synchronizer design for CAP-based VDSL system. It uses a digital spectral line method for the timing tone extraction and an adaptive loop filter with digitally controlled loop gain for the jitter performance improvement. They enable the robust and stable timing extraction from the severely distorted received signal. The prototype synchronizer is fabricated in a 0.6µm CMOS process. It provides 12.02psec RMS and 86psec peak-to-peak timing jitter, when operates at 40MHz, and makes the VDSL system receive data up to 52Mbps through the telephone wire.