A 0.8V, 9ns, 0.77mW at 50MHz, 128kb, four-way, set-associative, 2-level CMOS cache memory using two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swing (S

This paper presents a 0.8V, 128Kb, four-way, set-associative, 2-level CMOS cache memory using a novel two-stage WLOTC/BLOTC tag-compare scheme and sense wordlines/bitlines (SWL/SBL) tag sense amps with an 8-T tag cell in level 2 and a 10-T shrunk logic swing (SLS) memory cell with the ground/floating (G/F) data sense amp in level 1 for high-speed operation. Owing to the reduced loading at the sense word-line (SWL) in the new 11-T tag cell in L1 using WLOTC scheme and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amps and the SLS memory cell with G/F data sense amp in L1, implemented by a 1.8V 0.18µm CMOS technology, this 0.8V cache memory has an L1/L2 hit time of 6ns/11ns at the average power dissipation of 0.77mW at 50MHz.