Title :
A high-speed memory interface circuit tolerant to PVT variations and channel noise
Author :
Park, Joon-Young ; Koo, Yido ; Jeong, Deog-Kyoon ; Kim, Wonchan ; Yoo, Changsik ; Kim, Changhyun
Author_Institution :
Seoul National University, Seoul, Korea
Abstract :
A high-speed I/O circuit for the memory interface is implemented in a 0.25µm CMOS technology. To increase the sensitivity of the input circuit, the receiver employs the positive feedback. For driving of signal with the proper slew rate and specified voltage level under PVT variations, the pro-posed output circuit includes the novel level detection circuit and slew rate control scheme.
Conference_Titel :
Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European
Conference_Location :
Villach, Austria
