• DocumentCode
    439639
  • Title

    A high-speed memory interface circuit tolerant to PVT variations and channel noise

  • Author

    Park, Joon-Young ; Koo, Yido ; Jeong, Deog-Kyoon ; Kim, Wonchan ; Yoo, Changsik ; Kim, Changhyun

  • Author_Institution
    Seoul National University, Seoul, Korea
  • fYear
    2001
  • fDate
    18-20 Sept. 2001
  • Firstpage
    293
  • Lastpage
    296
  • Abstract
    A high-speed I/O circuit for the memory interface is implemented in a 0.25µm CMOS technology. To increase the sensitivity of the input circuit, the receiver employs the positive feedback. For driving of signal with the proper slew rate and specified voltage level under PVT variations, the pro-posed output circuit includes the novel level detection circuit and slew rate control scheme.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European
  • Conference_Location
    Villach, Austria
  • Type

    conf

  • Filename
    1471391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439639