Speed and behaviour improvement for semidynamic flip-flop logic family

Latency reduction is one of the first objective in Flip-Flop performances improvement if the application is an high pipelined architecture. The Semi-Dynamic Flip-Flop family is discussed in this paper and improved in terms of speed by adding two new transistors in the evaluation stage and in the data transfer stage respectively. The frequency is increased by a 1.76 factor (from 1.67GHz to 2.94 GHz). A cell library has been developed, optimized and characterized: it has then been proved by simulating a prescaler achieving as maximum frequency 2.6GHz.