A leakage tolerant high fan-in dynamic circuit design technique

We present a leakage tolerant dynamic circuit called Source Following Evaluation Gate (SFEG) which has high DC noise margin. Simulation results in 0.13µm and 0.1µm CMOS process technologies [1] show considerable degradation in noise immunity of domino circuits with threshold voltage scaling and/or increase of fan-in. Comparison with standard domino circuits indicates the noise immunity of 16-input OR SFEG is 37% higher than domino circuit with same delay. We also show that the noise characteristic of SFEG is insensitive to fan-in, and hence, the difference of noise immunity between SFEG and domino becomes larger with the increase in fan-in.