Scalable, power and area efficient high throughput Viterbi decoder implementations

Todays increasing demand for implementations featuring low power consumption and small area with adequate performance to comply with specifications requires a physical oriented design approach. In principle, a scalable platform based, physical optimized design library in combination with a flexible datapath generator establishes the basis for various physical design oriented implementations of high efficiency. As an example of a frequently used module for data reconstruction in digital communication systems, implementations of the Viterbi algorithm are presented applying this design approach and covering a broad range of high throughput rates from 50 Mbd up to 550 Mbd in a 0.25 µm CMOS technology. The development of a platform for scalable Viterbi decoder implementations is shown including quantitative optimization steps on different levels of design hierarchy. The resulting designs are compared to other leading edge Viterbi decoders approving this design style.