A 1-V, 10-MHz clock-rate, 13-bit CMOS Δ Σ modulator using unity-gain-reset opamps

A low-voltage ΔΣ modulator, incorporating unity-gain-reset opamps, is described. Due to the feedback structure, the opamps do not need to be switched off during operation, and hence can be clocked at a very high rate. A test chip, realized in a 0.35-µm CMOS process and clocked at 10.24 MHz, provided a dynamic range (DR) of 80 dB and a signal-to-noise+distortion-ratio (SNDR) of 78 dB for a 20-kHz signal bandwidth, and DR = 74 dB and SNDR = 70 dB for a 50-kHz BW.