• DocumentCode
    439697
  • Title

    A 12-bit power efficient continuous-time Σ Δ modulator with 250 µ W power consumption

  • Author

    Gerfers, F. ; Ortmanns, M. ; Manoli, Y.

  • Author_Institution
    University of Saarland, Saarbruecken, Germany
  • fYear
    2001
  • fDate
    18-20 Sept. 2001
  • Firstpage
    538
  • Lastpage
    541
  • Abstract
    This article presents the design and experimental results of a 3rd order lowpass ΣΔ modulator using a continuous-time loopfilter. The modulator was implemented in a 0.5µm 3.3 V CMOS technology with standard threshold voltages. The ΣΔ modulator feature 80dB dynamic range and a resolution of 12 bit in the bandwidth of 25kHz. The measured power consumption is only 250 µW from a single 1.5V supply.
  • Keywords
    Capacitance; Clocks; Coupling circuits; Delay; Energy consumption; Frequency conversion; Jitter; Power supplies; Resistors; Signal to noise ratio;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European
  • Conference_Location
    Villach, Austria
  • Type

    conf

  • Filename
    1471451
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439697