A 0.13- µm CMOS NOR flash memory experimental chip for 4-b/cell digital storage

This paper presents architectural and circuit solutions developed to achieve 4-b/cell storage in NOR-type Flash memories. A multiple closed-loop voltage sensing topology, combined with hierarchical load-decoupling row selection, and a two-step analog-to-digital conversion with early most significant bit (MSB) detection, achieve 120-ns access time for the stored MSBs. 80-mV programming step is provided by a switched-capacitor staircase waveform generator. Experimental data from a 0.13-µm CMOS test-chip are given.