Design of a 3D fully-depleted SOI computational RAM

We present a three-dimensional processor-in-memory integrated circuit that provides linearly increasing processing power, while incurring no extra design effort or mask sets as the number of stacked dies increases. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The test chip, with 128 kb of memory and 512 processing elements on two fully-depleted silicon-on-insulator dies, can achieve 170 billion bit-operations per second at 400 MHz.