A 6.7-fF/ µm2 bias-independent gate capacitor (BIGCAP) with standard CMOS process and its application to the loop filter of a differential PLL

A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance, which needs no additional fabrication process steps, is proposed. Measured results with 0.13-µm standard CMOS technology show that the intrinsic capacitance is 6.7 fF/µm²(6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (one-fifth that of typical MIM capacitors). The linearity is ±2.9% and capacitance variation across a wafer is as small as σ = 0.096%. Applying BIGCAP to the loop filter of a differential PLL reduces the gate area of the MOS capacitor for the loop filter to only 35% of that of the conventional design without degrading the performance of the PLL. The measured jitter at 840 MHz was 7.0 ps (rms) and 74.4 ps (p-p) for 1.5- V supply.